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stb02_sds_0327.fm.01 march 27, 2000 ibm39stb0210x advance stb0210x digital set-top box integrated controllers features page 1 of 39 features overall ? ibm set-top box technology ? four major subsystems integrated with ibm on- chip coreconnect ? structure. ? maximum mips for os and application tasks ? simpli?ed driver and software development ? scalable, ?exible, and extendible ? 54 mhz/57 mips ? 3.3 v and 2.5 v power supplies ? ibm cmos sa-12e process(0.25 m m) ? 352-pin pbga package mpeg-2 digital audio/video subsystem ? mpeg-2 video decoder ? mpeg-2 audio decoder ? mpeg-2 transport/dvb descrambler ? macrovision copy protection on selected parts ? display controller ? digital encoder (denc) with six outputs ? anti-flicker filter powerpc 401 ? host processor: ppc401b3 cpu ? 16kb instruction, 8kb data caches ? universal interrupt controller memory subsystem ? dma controller ? cross-bar switch ? external bus interface unit (ebiu) ? ide interface ? one sdram controller peripheral subsystem ? general purpose timers (gpts) ? pulse width modulators ? smart card controller ?i 2 c interface ? 16550 serial communications port ? infrared serial communications port ? general purpose inputs/outputs ? serial controller port ? modem serial interface/digital audio input description ibm stb0210x digital set-top box integrated con- troller family are highly integrated silicon devices specifically developed for digital set-top box (stb) applications using industry-leading ibm cmos sa- 12e (0.25 m m) process technology. the stb0210x is part of the second generation of ibm products for digital stb applications. powerpc processing and peripheral i/o architecture provide a high level of performance and functionality when used in audio and video subsystems. the resulting stb technology is full-functioned and easy to use. the stb0210x minimizes host processor interven- tion to maximize mips for operating system and application tasks. most of the features required in the back end of typical midrange and high-end stbs are integrated. driver and software develop- ment is facilitated while preserving scaleability, flex- ibility, and extendibility. architecturally, the devices consist of four sub- systems interconnected and tuned using corecon- nect, the ibm multiple-bus, on-chip interconnect structure: 1. powerpc host processor 2. digital audio/video 3. memory interface 4. peripheral these high performance subsystems are suited for interactive stbs with demanding software require- ments.
ibm39stb0210x stb0210x digital set-top box integrated controllers advance ordering information page 2 of 39 stb02_sds_0327.fm.01 march 27, 2000 conventions and notation throughout this document, standard ibm notation is used, meaning that bits and bytes are numbered in ascending order from left to right. thus, for a 4-byte word, bit 0 is the most significant bit and bit 31 is the least significant bit. overbars, e.g. txenb, designate signals that are active low. numeric notation is as follows: hexadecimal values are in single quotes and preceded by "x" or "x." for example: x0b00. binary values are spelled out (zero and one) or appear in single quotes and preceded by a "b." for example: b10101. settings of a bit or field are binary numbers but are often displayed in tabular form without quotes or the pre- ceding "b." for example: 00 : 30 frames per second 01 : 15 frames per second 11 : 10 frames per second ordering information part number performance (est.) clock speed audio copy protection ibm39stb02100pba22c 57 mips 54 mhz mpeg none IBM39STB02101PBA22C 1 macrovision 1. these parts support macrovision copy protection and require that a license be in effect between the purchaser and macrovision corporation. please see macrovision licensing on page 3.
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 licensing requirements page 3 of 39 licensing requirements macrovision licensing macrovision copy protection is supported in the ibm39stb02101 product. these devices are protected by u.s. patent numbers 4,631,603, 4,577,216, and 4,819,098 and other intellectual property rights. the use of macrovisions copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. a valid macrovision license must be in effect between the stb02101 purchaser and macrovision corporation. additional per-chip royalties may be required and are to be paid by the purchaser to macrovision corporation. macrovision corporation 1341 orleans avenue sunnyvale, ca 94089
ibm39stb0210x stb0210x digital set-top box integrated controllers advance architecture and subsystem information page 4 of 39 stb02_sds_0327.fm.01 march 27, 2000 architecture and subsystem information block diagram opb bridge ppc401b3 16k-i cache 8k-d cache dma controller video decoder 2d/3d graphics nim descrambler audio d/a plb0 plb1 crossbar dvb descrambler audio decoder trace flash transport jtag opb bus serial1/ gpt serial modem i 2 c0 gpio sdram1 sdram smart card1 ext digital interrupts perh device sram serial0/ 16550 infrared control port interface ebiu controller pwm ide uic rom osd dac encoder digital encoder cpu iec-60958
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 architecture and subsystem information page 5 of 39 powerpc 401b3 host processor subsystem the powerpc 401b3 (ppc401b3) subsystem handles all system initialization and control and also provides power and flexibility for product differentiation. powerpc 401b3 cpu the ppc401b3 provides high performance and low power consumption. the cpu executes at sustained speeds of greater than one cycle per instruction at 54 mhz. interrupt latency is three cycles, the best time for critical interrupts. ppc401b3 subsystem risc execution unit cache timers: pit, fit, 64-bit base core clocking multiplier/divider thirty-two 32-bit gprs cpu ppc401b3 processor plb master controls cache controls 8kb i-cache array interrupt controller interface interfaces uic interrupts plb master clocks power mgmt dcrs jtag (see note) note: the jtag interface is used for development. 16kb d-cache array data instruction mmu
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 architecture and subsystem information page 6 of 39 on-chip instruction is compatible with powerpc user instruction set architecture. there are 32 x 32 bit gen- eral purpose registers. instruction and data cache arrays improve system throughput. the cpu has a sepa- rate two-way set-associative 16kb instruction cache and an 8kb write-back/write-through data cache. multiply and divide instructions are performed in hardware and are not emulated in software. universal interrupt controller the universal interrupt controller (uic) provides all necessary control, status, and communication functions between all sources of interrupts and the ppc401b3. the uic combines stb0210x interrupts and presents them to the ppc401b3s critical or non-critical inputs. all interrupts can be programmed to generate either critical or non-critical output. interrupts can be level- or edge-sensitive and interrupt polarity is programmable. an optional read-only vector is used to reduce critical interrupt servicing latency. this vector is generated by combining an offset (based on the bit position of the highest priority, enabled, and active critical interrupt) and a vector base address register. a configurable priority control bit determines whether the least significant or most significant bit in the status register has the highest priority. clock and power management for power-saving purposes, a clock and power management (cpm) input is used to shut down clocks and device functions. a reset is required to activate a unit. memory interface subsystem the memory interface subsystem provides the system memory controller interface for sram, flash mem- ory, rom, and sdram. it also provides the direct memory access (dma) interfaces for these memories. direct memory access controller the four-channel dma controller is a processor local bus master that allows faster data transfer between memory and peripherals than with program control. the controller supports memory-to-memory, peripheral- to-memory, and memory-to-peripheral transfers. the dma controller allows the ppc401b3 processor to exe- cute instructions with no bus contention when the ppc401b3 is executing from cache. dma is useful when the overhead associated with the controller setup is minimal compared to the time it would take to move data using program control load and store instructions. memory subsystem plb1 plb0 dma sdram1 sdram crossbar ebiu flash, rom, etc.
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 architecture and subsystem information page 7 of 39 each dma channel has an independent set of registers for data transfer. the registers store data for control, source address, destination address, and transfer count. each channel also supports chained dma opera- tions, therefore every channel also includes a chained count register in which case source address registers function as chained address registers. all dma channels report their status to the dma execution unit. the dma controller also supports: ? internal dma channels for smart card interface, 16550 serial communications controller, infrared commu- nications controller, etc. ? 16- and 32-bit peripherals (on-chip peripheral bus and external) ? 32-bit addressing ? address increment or decrement ? internal data buffering capability ? memory-mapped peripherals processor local bus the processor local bus (plb) interfaces directly with the ppc401b3 and the other major subsystems (see block diagram, on page 4). the stb0210x uses two plbs to provide high bandwidth between the function masters and the external memory interfaces for rom, flash, and sdram, etc. the stb0210x plb architec- ture includes a crossbar switch to present both memory interfaces as flat, shared memory spaces . external bus interface unit the external bus interface unit (ebiu) expands the local bus to transfer data between the plb and a wide range of memory and peripheral devices attached to the external bus (see the following list). the ebiu can control up to eight devices or banks or regions of flash memory (128 mb), and a low latency maximizes system performance. the ebiu supports: ? a direct connect sram/rom/pia interface for - up to eight sram/rom/pia banks with programmable address select - programmable or device-paced wait states - burst mode (bme) and single-cycle transfers ? 16- and 32-bit byte addressable bus width ? programmable target word ?rst or sequential cache line ?lls ? dvb common interface support ? ide interface supports: - ata-3 mode 4, register, and pio - mode 2 multiword dma transfers (see ansi x3.298-1997, at attachment-3 interface (ata-3)) - multi-word dma (15.5 mb/s maximum transfer rate) ? external bus master with support for device master and master/slave ? common bank-speci?c programmability ? device-paced ready input sdram controller the sdram controller transfers data between the plb and up to two sdram memory banks attached to the external bus. the controller implements address and data pipelining and supports 16mb and 64mb sdrams concurrently. it also provides the following: ? direct-connect sdram interface
ibm39stb0210x stb0210x digital set-top box integrated controllers advance architecture and subsystem information page 8 of 39 stb02_sds_0327.fm.01 march 27, 2000 ? high bandwidth with a narrow 16-bit interface ? page interleaving ? programmable address select ? programmable rates for automatic sdram refresh ? software-initiated and self refresh modes for power savings crossbar switch the plb crossbar switch (cbs) creates a flat memory model and implements unified memory architecture (uma), which connects multiple plb master buses to the plb slave buses, thus allowing two sets of plb buses to intercommunicate. processor, transport, and the audio and video decoders can access memory through the memory controller. digital audio/video subsystem the mpeg-2 digital audio/video subsystem provides fully-synchronized playback of digital video and audio programs, with a minimum of interaction from the ppc401b3 processor. mpeg-2 video decoder with osd the mpeg-2 video decoder provides decompression, decoding, and synchronized playback of digital video streams with a minimum of host support. it produces interlaced video output and can support mpeg-2 com- pressed data streams up to an average rate of 15 mbps. the video decoder is also backward compatible to support the iso/iec international standard 11172-2 (11/93) (also called mpeg-1 standard). it supports the iso/iec 13818-2 main profile at main level. the decoder also supports mpeg-2 mp@ml compliance with 2mb memory. only 2mb of memory are needed to decode full ccir601 resolution ntsc and pal encoded mpeg-2 bitstreams. it performs real-time decoding of all resolutions in 16-pixel multiples, up to and including 720x480x30 or 720x576x25. horizontal and vertical ?lters deliver high-quality video. chrominance ?ltering and up-sampling to provide ccir601 4:2:2 video output. pan and scan are supported in 1/16 pel accuracy for 16:9 source material. video rates range from 1.5 mbps to 15 mbps (higher in bursts). plb1 plb0 mpeg-2 video decoder osd mpeg-2 audio decoder mpeg-2 transport dvb descrambler denc audio pll vcxo auxiliary auxiliary port nim to audio d/a and iec60958
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 architecture and subsystem information page 9 of 39 the mpeg-2 video decoder supports the european dvb standard and accepts packetized elementary or elementary mpeg-2 streams. it uses packetized elementary stream (pes) video decoding to extract the presentation time stamp (pts), and handles user data and other pes layer bit fields through memory access from the ppc401b3. input can be from transport or directly from system memory. outputs are pro- vided for video-only and for video-with-osd. the decoder can insert data in the vertical blanking interval (vbi) with vbi output support. it supports decod- ing of still or fixed images and display of scaled video images. it also features: ? letterbox format display ? selectable anti-?icker ?ltering ? output interface ?exibility (programmable controls) ? composite blanking and field id signals ? v-sync and h-sync signals ? ccir656 master and slave modes ? programmable signal polarity ? sophisticated error concealment ? 3:2 pull-down support. ? closed caption, teletext, or mixed (vps) ? (1/4x, 1/2x, 2x) and three graphic planes ? automated video channel change and time-base change features ? blending of external graphics. a multi-plane on-screen display (osd) uses bitmap data in memory to be merged with or displayed in place of the motion video data. three osd planes (the cursor, graphics and image planes) are provided for increased display flexibility. the osd includes: ? programmable background color ? multi-region link list graphic and image plane osd with a color table for each region ? programmable bitmap resolution on a region-by-region basis ? 64 x 64 pixel, 16-color cursor plane with blending controls ? overlay and video blending of graphic plane ? enhanced color mode for 24-bit color (yuv) in direct color and clut modes with 8-bit alpha blending ? video shading in graphic plane osd area ? osd control output for external multiplexer (picture-in-picture support) ? tiling capability in image and graphic planes ? scrolling of image and graphic planes ? horizontal scaling of image plane bitmaps ? animation support ? 16 mb osd addressing range to support more and larger bitmaps. mpeg-2 transport and dvb descrambler the mpeg-2 transport demultiplexer provides iso / iec 13818-1 mpeg-2 transport system layer demulti- plexing. its integrated digital video broadcasting (dvb) descrambler complies with dvb system layer require- ments and may be turned off for non-dvb applications. peak input rates are 100-mbps (parallel) or 60-mbps (serial), or 88-mbps (parallel) or 60-mbps (serial) with the optional descrambler. packet identifier (pid) filter- ing is based on 32 programmable entries with detection and notification of errors and lost packets. hardware- based clock recovery on program clock references (pcrs) reduces processor load by: - calculating clock difference between pcr and system time clock (stc) - modulating output to drive an external vcxo - using an optional internal clock-recovery algorithm based on clock difference
ibm39stb0210x stb0210x digital set-top box integrated controllers advance architecture and subsystem information page 10 of 39 stb02_sds_0327.fm.01 march 27, 2000 transport and descrambler features include: ? internal dvb (1.0 or 1.1) descrambler, including ?ltering and storage of eight control word pairs ? auxiliary output port for real-time data transfers: - 8-bit mode at 1x, 1/2x, 1/3x, 1/4x and 1/8x of the system clock speed ? table section ?ltering: - 64 separate 4-byte ?lter blocks with bit-level masking with full match/not match capability - multiple ?lters can be linked to extend ?ltering depth in 4-byte increments - multiple ?lters per pid - filters program-speci?c information (psi), service information (si), private tables - handles multiple sections per packet and sections that span packets - optional crc checking of section data ? selective routing of some or all packet data to system memory: - based on 32 separate queues (one per pid) - routing entire packets, payloads, adaptation ?elds, table sections (after ?ltering) and private data ? direct transfer of audio / video (pes) data to decoders ? simpli?ed channel changes, time-base changes and error ?agging / concealment through direct commu- nication with decoders mpeg-2 audio decoder the audio decoder receives and decodes either es (elementary stream) or pes (packetized elementary stream) audio data. the audio compute engine is a generic dsp processor that decodes mpeg, or 16-, 18- or 20-bit unformatted pulse code modulation (pcm) audio data via individual software programs. the host processor downloads each program load to the audio decoder following initialization. the audio decoder generates up to two channels of decoded pcm for mpeg and pcm audio playback output. it pro- vides 2-channel mpeg audio to two channels output. unpacketized pcm (upcm) plays back at sampling fre- quencies of 16 khz, 22.05 khz, 24 khz, 32 khz, 44.1 khz, and 48 khz, along with quantization sample width selections of 16-, 18-, or 20-bit input and 16 or 20-bit output. the audio decoder: ? decodes mpeg-1 and mpeg-2 audio, layers i and ii and 2-channel output, including single channel, stereo, joint stereo, and dual channel modes. ? performs mpeg-1 and mpeg-2 pes audio parsing, and also accepts audio elementary streams. parses and stores ancillary data into external memory for later use by the host processor. ? supports 16-khz, 22.05-khz, 24-khz, 32-khz, 44.1-khz, and 48-khz audio sampling frequencies. ? supports audio/video synchronization through pts/stc comparison with each audio frame. ? supports an encoded audio bit rate up to 640 kbps. this bit rate only pertains to encoded bitstream data. ? includes audio clip mode for pes, es, and pcm formats with byte address granularity and 2mb maxi- mum per clip buffer. ? supports expandable rate buffer size selectable from 4k to 64k (in 4k increments). ? uses a re-locatable rate buffer region, with a programmable base register (128-byte location granularity). ? has a re-locatable pts value and ancillary data region, using a programmable base register with 128- byte location granularity.
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 architecture and subsystem information page 11 of 39 ? uses a locatable audio temporary data and decoded audio data bank region (programmable base reg- ister with 128-byte location granularity with additional offset register). ? includes 256x and 512x dac sampling clock frequency con?gurations. ? has a programmable stream id register with corresponding 8-bit enable ?eld. ? provides three pcm output formats in 16- or 20-bit precision: -i 2 s - left-justi?ed - right-justi?ed ? performs audio bitstream error concealment, either by frame repeats or muting, due to loss of synchroni- zation or detection of crc errors. ? performs mpeg error checking using frame size calculation for each frame. ? provides a programmable interface that supports the following: - play, stop, and mute - rate buffer purge to support channel and mode changes - provides compressed buffer empty/full indicators - synchronization enable/disable for pts-stc comparison - provides buffer fullness value ? includes spdif meeting iec61937 specs. ? supports enhanced iec61937 s/p dif channel status bit by including 16 spdif channel status bits, with host control over most of the bits. ? inserts host-controlled validity bit into spdif sub-frame via dcr register. ? performs audio attenuation in 64 steps, with smooth transitions between steps. ? provides tone generation with up to 128 generated tones at 31 different durations with seven levels of attenuation via processor command. ? supports automated channel change. ? supports automated time base change. ntsc/pal digital encoder unit with macrovision copy protection 1 the multi-standard digital encoder converts digital audio/video data into analog national television system committee (ntsc) or phase alternate line (pal) data output formats (see macrovision licensing on page 3). it provides up to six concurrent analog video outputs, including s-video, composite video, ypbpr, and rgb. the encoder is compatible with scart connectors, with support for macrovision copy protection revi- sion 7. analog outputs are driven by 10-bit d/a converters, operating at 27 mhz. the outputs drive standard video levels into 75- w loads. it s upports closed caption, teletext insertion, and line 23 wss (wide-screen signaling) per itu-r bt.1119. there is a switchable pedestal with gain compensation. playback of synchro- nized video data can be locked to the incoming composite video stream. 1. this feature is available only on stb02101, macrovision license required.
ibm39stb0210x stb0210x digital set-top box integrated controllers advance architecture and subsystem information page 12 of 39 stb02_sds_0327.fm.01 march 27, 2000 additional interfaces external graphics and video (egv) port external graphics and video (egv) ports provide flexibility for interfacing external graphics and video compo- nents. when the egv is used as an output, its signals may be routed to an external graphics device or denc. when used as an input, either the internal osd graphics can be replaced with data from an external graphics device, or external digital video data (from an analog signal converted to digital via dsmd, for exam- ple) could replace the internally decoded mpeg video. in the latter case, the external digital video can be merged/blended with the internal osd graphics. peripheral subsystem general purpose timer the general purpose timer (gpt) is an on-chip peripheral bus (opb) function that provides a separate time base counter and additional system timers beyond those defined in the ppc401b3. three inter-character (ic) time-out timers are also implemented in this functional unit in the gpt. these tim- ers receive the count signal inputs from other units they are timing. each timer is a 10-bit down counter loaded with a programmable value (tout) upon the active edge of the count signal input. once loaded, the ic timer counts down tout number of tclk cycles until it reaches zero (that is, when the ic timer has expired). when a timer expires, it sets its corresponding bit in the ic interrupt status register. there is a separate time base inside the gpt, distinct from the time base within the ppc401b3. two event timers capture unique input events and there are two compare timers with unique outputs. separately config- urable and programmable synchronization controls edge detection and output levels. there are two reset inputs, one for the entire gpt unit, and one for the time base. opb peripheral subsystem other subsystems gpt / pwm smartcard iic 16550 serial com infrared serial com gpio serial control port ibm stb0210x modem interface plb0 opb bridge
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 architecture and subsystem information page 13 of 39 pulse width modulation the pulse width modulation (pwm) function produces two square wave outputs with a variable duty cycle under program control. the duty cycle varies from 100 percent to zero percent in steps of 1/256. there is a control register with two bits for each pwm. this register controls the active status of the pwm, and deter- mines what its inactive output level should be. when the pwm control register is set to disable a pwm, the 8- bit period counter will be inactive to minimize power. the pulse width modulation portion of the gpt contains two identical blocks, each containing an 8-bit pro- grammable and reloadable down counter and control logic. a time-base generator that is a free-running counter (tclk based) generates the frequency of the pulse-width modulated output. iinter-integrated circuit (iic) unit the iic unit is used to provide a simple to use, highly programmable interface between the opb and the industry standard iic serial bus. they provide full management of all iic bus protocols, compliant with phillips semiconductors i 2 c speci?cation, dated 1995, and support a ?xed v dd iic interface. it can be programmed to operate as master, as slave, or as both master and slave on the iic interface. in addition to sophisticated iic bus protocol management, the iic provide full data buffering between the opb and the iic bus. the iic unit offers 5 v tolerant i/o for both 100- and 400-khz operation with 8-bit data transfers and 7-bit and 10-bit address decode/generation. there is one programmable interrupt request signal, two independent 4 x 1-byte data buffers, and 12 memory-mapped, fully programmable configuration registers. smart card interface unit the smart card interface unit handles communications between an integrated circuit card and the host cpu. these 5 v tolerant i/o devices have a software-based control structure and are designed for use with asynchronous transmissions. it features hardware activation/deactivation and reset with software overrides and byte-wide fifo support. it is compatible with iso/iec 7816-3 and support t0 and t1 protocols. the interface unit support 2-channel dma with 8-bit memory-mapped registers and hardware error checking. an inter-character time-out facility provides timing support from the gpt/pwm. 16550 serial communication controller the 16550 serial communication controller is a universal asynchronous receiver/transmitter (uart) with fifos, and is compatible with the 16550 part numbers manufactured by national semiconductor (ns) corpo- ration. it is also compatible with national semiconductor 16450 (non-fifo version). serial interface charac- teristics are fully programmable with complete modem control functions and status reporting capability. the controller supports: ? 5-, 6-, 7-, or 8-bit characters ? even, odd, or no parity bit generation and detection ? 1-, 1.5-, or 2-stop-bit generation ? variable baud rate and a programmable baud rate generator there is also support for two dma channels with a 16-byte fifo for transmit/receive path. internal loopback is provided for diagnostics and an inter-character timeout facility provides timing support from the gpt/pwm.
ibm39stb0210x stb0210x digital set-top box integrated controllers advance architecture and subsystem information page 14 of 39 stb02_sds_0327.fm.01 march 27, 2000 infrared serial communications controller in addition to standard uart functions, the serial/infrared communications controller can use an alternate mode (irda mode) to transfer and receive infrared characters. irda transmissions are specified by the infra- red data association (irda) specification 1.1. irda mode supports rs-232 and infrared communications up to 1.152 mbps with automatic insertion/removal of standard async communication bits. the controller includes: ? a programmable baud rate generator ? individual enable for receiver and transmitter interrupts ? internal loopback and auto-echo modes ? full-duplex operation ? programmable serial interface ? status reporting capability ? individual receiver and transmitter dma support ? auto-handshaking mode for receiver and transmitter ? transmitter pattern generation capability ? serial clock frequency up to 1/2 system clock frequency ? inter-character timeout facility support from the gpt/pwm modem interface the modem interface provides a glueless communication from the device to and from many standard and economical telephony codecs (note: codecs are the audio adc/dac devices). the ppc401b3 cpu and applicable software can be used to implement an inexpensive interface for a modem. the external interface supports industry standard 4-wire parameters, consisting of transmit data, receive data, clock, and frame sync. two channels of dma allow off-loading data from the cpu. the modem interface supports digital audio mic input, status reporting, and interrupt generation. serial control port the serial control port (scp) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other scp bus-compatible serial devices. the scp is a slave device to the opb bus, and supports a three-wire interface to the serial port (receive, transmit, and clock). it provides a glueless serial interface to many microcontrollers, with clock inversion and reverse data. the port includes a program- mable clock rate divider (sysclk/4 to sysclk/1024), and bit rate is supported up to 1/4 the frequency of the system clock. general purpose i/o controller the general purpose i/o (gpio) controller enables the multiplexing of module i/os, with functions that include programmable open-drain output conversion, registered input and output functions, and simplified gpio definition.
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 15 of 39 pin and i/o information pinout diagram ac ab aa y w v u t r p n m l k j h g f e d c b a v dd25 ground i/o pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 v dd33 legend: 19 20 21 22 23 24 25 26 af ae ad
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 16 of 39 stb02_sds_0327.fm.01 march 27, 2000 signal pins sorted by signal name signal grid (pin) position group signal grid (pin) position group aud_vdda0 af15 pll analog pwr + gnd bi_data2 ad16 bus interface aud_vdda1 ae12 pll analog pwr + gnd bi_data3 ad15 bus interface bi_address8 (msb) af11 bus interface bi_data4 ae15 bus interface bi_address9 ad10 bus interface bi_data5 ae16 bus interface bi_address10 ae10 bus interface bi_data6 ae17 bus interface bi_address11 ae9 bus interface bi_data7 af19 bus interface bi_address12 ac9 bus interface bi_data8 ae18 bus interface bi_address13 ae11 bus interface bi_data9 ac17 bus interface bi_address14 ad4 bus interface bi_data10 af16 bus interface bi_address15 af4 bus interface bi_data11 ad14 bus interface bi_address16 ae5 bus interface bi_data12 af14 bus interface bi_address17 ac5 bus interface bi_data13 ad13 bus interface bi_address18 ac7 bus interface bi_data14 af18 bus interface bi_address19 ad6 bus interface bi_data15 ae20 bus interface bi_address20 ad7 bus interface bi_data16 ad25 bus interface bi_address21 ae8 bus interface bi_data17 ad23 bus interface bi_address22 ad9 bus interface bi_data18 ae23 bus interface bi_address23 ac10 bus interface bi_data19 ae22 bus interface bi_address24 af9 bus interface bi_data20 ad19 bus interface bi_address25 af8 bus interface bi_data21 af21 bus interface bi_address26 ae7 bus interface bi_data22 ad21 bus interface bi_address27 af6 bus interface bi_data23 ae26 bus interface bi_address28 af5 bus interface bi_data24 ae24 bus interface bi_address29 ae3 bus interface bi_data25 ad22 bus interface bi_address30 af3 bus interface bi_data26 af22 bus interface bi_address31 (lsb)/bi_wbe1 af2 bus interface bi_data27 ac20 bus interface bi_cs0 ad11 bus interface bi_data28 ac19 bus interface bi_cs1 af13 bus interface bi_data29 af20 bus interface bi_cs2 ab3 bus interface bi_data30 af24 bus interface bi_cs3 ac1 bus interface bi_data31 ad26 bus interface bi_data0 (msb) ae19 bus interface bi_oe ae13 bus interface bi_data1 ad17 bus interface bi_ready ac12 bus interface
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 17 of 39 bi_r w ae14 bus interface dac1_rout c14 video and graphics bi_wbe0 ad12 bus interface dac1_rref_out a9 video and graphics ci_clock f26 channel interface dac1_vref_in c10 video and graphics ci_data0 (msb) c25 channel interface dac2_agnd0 b13 dac analog pwr + gnd ci_data1 d24 channel interface dac2_agnd1 b16 dac analog pwr + gnd ci_data2 g23 channel interface dac2_agnd2 d18 dac analog pwr + gnd ci_data3 a24 channel interface dac2_avdd0 a14 dac analog pwr + gnd ci_data4 e26 channel interface dac2_avdd1 c16 dac analog pwr + gnd ci_data5 b24 channel interface dac2_avdd2 d17 dac analog pwr + gnd ci_data6 g26 channel interface dac2_avdd3 c19 dac analog pwr + gnd ci_data7 (lsb) e24 channel interface dac2_bout a19 video and graphics ci_data_enable h24 channel interface dac2_bref_out b19 video and graphics clk_vdda ac2 pll analog pwr + gnd dac2_gout b15 video and graphics da_bit_clock p1 audio dac2_gref_in d15 video and graphics da_iec_958 m3 audio dac2_rout c15 video and graphics da_lr_channel_clock m4 audio dac2_rref_out b18 video and graphics da_oversampling_clo ck p2 audio dac2_vref_in b17 video and graphics da_serial_data0 r2 audio dv1_data0 (msb) c5 video and graphics dac1_agnd0 d13 dac analog pwr + gnd dv1_data1 b5 video and graphics dac1_agnd1 b10 dac analog pwr + gnd dv1_data2 c8 video and graphics dac1_agnd2 d8 dac analog pwr + gnd dv1_data3 b4 video and graphics dac1_avdd0 b12 dac analog pwr + gnd dv1_data4 c6 video and graphics dac1_avdd1 b11 dac analog pwr + gnd dv1_data5 c4 video and graphics dac1_avdd2 d10 dac analog pwr + gnd dv1_data6 b3 video and graphics dac1_avdd3 c9 dac analog pwr + gnd dv1_data7 (lsb) a4 video and graphics dac1_bout b7 video and graphics dv1_hsync a8 video and graphics dac1_bref_out a7 video and graphics dv1_pixel_clock a6 video and graphics dac1_gout a11 video and graphics dv1_vsync a3 video and graphics dac1_gref_out c13 video and graphics g_system_clock ac3 global signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 18 of 39 stb02_sds_0327.fm.01 march 27, 2000 g_system_rst g3 global gpio_5 c23 general purpose i/o gnd p23 ground gpio_6 y4 general purpose i/o gnd v4 ground gpio_7 aa1 general purpose i/o gnd a1 ground gpio_8 w3 general purpose i/o gnd a2 ground gpio_9 l2 general purpose i/o gnd a26 ground gpio_10 k3 general purpose i/o gnd ac4 ground gpio_11 g2 general purpose i/o gnd ac8 ground gpio_12 m2 general purpose i/o gnd ac13 ground gpio_13 l3 general purpose i/o gnd ac18 ground gpio_14 h1 general purpose i/o gnd ac23 ground gpio_15 n2 general purpose i/o gnd ad3 ground gpio_16 aa25 general purpose i/o gnd ad24 ground gpio_17 y23 general purpose i/o gnd ae1 ground gpio_18 a22 general purpose i/o gnd ae2 ground gpio_19 d20 general purpose i/o gnd ae25 ground gpio_20 c21 general purpose i/o gnd af1 ground gpio_21 b21 general purpose i/o gnd af25 ground gpio_22 b20 general purpose i/o gnd af26 ground gpio_23 a21 general purpose i/o gnd b2 ground gpio_24 a16 general purpose i/o gnd b25 ground gpio_25 b14 general purpose i/o gnd b26 ground gpio_26 a12 general purpose i/o gnd c3 ground gpio_27 c12 general purpose i/o gnd c24 ground gpio_28 c11 general purpose i/o gnd d4 ground gpio_29 j2 general purpose i/o gnd d9 ground gpio_30 ab1 general purpose i/o gnd d19 ground gpio_31 ab2 general purpose i/o gnd d23 ground i2c0_scl n1 inter-integrated circuit ) gnd h4 ground i2c0_sda n3 inter-integrated circuit gnd j23 ground int0 ac24 interrupt gnd n4 ground int1 c26 interrupt gnd d14 ground int2 ad2 interrupt gnd w23 ground int3 ad1 interrupt gpio_2 b9 general purpose i/o mux1_0 ab25 multiplexed i/o gpio_3 ab26 general purpose i/o mux1_1 ab23 multiplexed i/o gpio_4 p26 general purpose i/o mux1_2 ac26 multiplexed i/o signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 19 of 39 mux2_0 c2 multiplexed i/o sd1_clk r23 sdram1 controller mux2_1 d1 multiplexed i/o sd1_cs0 n26 sdram1 controller mux2_2 e4 multiplexed i/o sd1_data0 (msb) aa26 sdram1 controller mux2_3 e1 multiplexed i/o sd1_data1 y24 sdram1 controller mux3_0 v2 multiplexed i/o sd1_data2 w26 sdram1 controller mux3_1 v1 multiplexed i/o sd1_data3 v25 sdram1 controller mux3_2 p3 multiplexed i/o sd1_data4 v24 sdram1 controller mux3_3 u3 multiplexed i/o sd1_data5 u25 sdram1 controller mux3_4 u2 multiplexed i/o sd1_data6 u24 sdram1 controller mux3_5 u4 multiplexed i/o sd1_data7 t26 sdram1 controller mux3_6 t3 multiplexed i/o sd1_data8 u23 sdram1 controller mux3_7 t2 multiplexed i/o sd1_data9 t25 sdram1 controller mux3_8 t1 multiplexed i/o sd1_data10 u26 sdram1 controller mux3_9 r3 multiplexed i/o sd1_data11 v26 sdram1 controller mux3_10 r1 multiplexed i/o sd1_data12 v23 sdram1 controller reserved (tie to 3.3v) f3 global sd1_data13 w25 sdram1 controller sc0_clk y2 smart card interface 0 sd1_data14 y25 sdram1 controller sc0_detect y1 smart card interface 0 sd1_data15 (lsb) aa24 sdram1 controller sc0_io w4 smart card interface 0 sd1_dqmh p25 sdram1 controller sc0_reset w1 smart card interface 0 sd1_dqml t24 sdram1 controller sc0_vcc_command w2 smart card interface 0 sd1_ras n25 sdram1 controller sd1_address0 (msb) m25 sdram1 controller sd1_we r25 sdram1 controller sd1_address1 n24 sdram1 controller serial1/infrared_cts f2 serial1 / infrared sd1_address2 p24 sdram1 controller serial1/infrared_rts d36 serial1 / infrared sd1_address3 m26 sdram1 controller serial1/infrared_rxd g4 serial1 / infrared sd1_address4 l25 sdram1 controller serial1/infrared_txd c1 serial1 / infrared sd1_address5 m24 sdram1 controller vdd25 aa4 2.5 v power sd1_address6 k23 sdram1 controller vdd25 aa23 2.5 v power sd1_address7 k24 sdram1 controller vdd25 ac6 2.5 v power sd1_address8 j26 sdram1 controller vdd25 ac11 2.5 v power sd1_address9 h26 sdram1 controller vdd25 ac16 2.5 v power sd1_address10 j25 sdram1 controller vdd25 ac21 2.5 v power sd1_address11 l24 sdram1 controller vdd25 d6 2.5 v power sd1_address12 k25 sdram1 controller vdd25 d11 2.5 v power sd1_address13 (lsb) l26 sdram1 controller vdd25 d16 2.5 v power sd1_cas r24 sdram1 controller vdd25 d21 2.5 v power signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 20 of 39 stb02_sds_0327.fm.01 march 27, 2000 vdd25 f4 2.5 v power vdd33 ac14 3.3 v power vdd25 f23 2.5 v power vdd33 ac15 3.3 v power vdd25 l4 2.5 v power vdd33 ad18 3.3 v power vdd25 l23 2.5 v power vdd33 ac22 3.3 v power vdd25 t4 2.5 v power vdd33 ab24 3.3 v power vdd25 t23 2.5 v power vdd33 y26 3.3 v power vdd33 e3 3.3 v power vdd33 w24 3.3 v power vdd33 g1 3.3 v power vdd33 r26 3.3 v power vdd33 h3 3.3 v power vdd33 n23 3.3 v power vdd33 m1 3.3 v power vdd33 m23 3.3 v power vdd33 p4 3.3 v power vdd33 j24 3.3 v power vdd33 r4 3.3 v power vdd33 e23 3.3 v power vdd33 v3 3.3 v power vdd33 c22 3.3 v power vdd33 ab4 3.3 v power vdd33 a20 3.3 v power vdd33 ad5 3.3 v power vdd33 a15 3.3 v power vdd33 af7 3.3 v power vdd33 d12 3.3 v power vdd33 ad8 3.3 v power vdd33 d5 3.3 v power vdd33 af12 3.3 v power vdd33 b8 3.3 v power vdd33 c7 3.3 v power signal pins sorted by signal name (continued) signal grid (pin) position group signal grid (pin) position group
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 21 of 39 . signal pins sorted by pin number grid (pin) position signal group grid (pin) position signal group a1 gnd ground b10 dac1_agnd1 dac analog pwr + gnd a2 gnd ground b11 dac1_avdd1 dac analog pwr + gnd a3 dv1_vsync video and graphics b12 dac1_avdd0 dac analog pwr + gnd a4 dv1_data7(lsb) video and graphics b13 dac2_agnd0 dac analog pwr + gnd a5 b14 gpio_25 general purpose i/o a6 dv1_pixel_clock video and graphics b15 dac2_gout video and graphics a7 dac1_bref_out video and graphics b16 dac2_agnd1 dac analog pwr + gnd a8 dv1_hsync video and graphics b17 dac2_vref_in video and graphics a9 dac1_rref_out video and graphics b18 dac2_rref_out video and graphics a10 nc b19 dac2_bref_out video and graphics a11 dac1_gout video and graphics b20 gpio_22 general purpose i/o a12 gpio_26 general purpose i/o b21 gpio_21 general purpose i/o a13 nc b22 nc a14 dac2_avdd0 dac analog pwr + gnd b23 nc a15 vdd33 3.3 v power b24 ci_data5 channel interface a16 gpio_24 general purpose i/o b25 gnd ground a17 nc b26 gnd ground a18 nc c1 serial1/infrared_txd serial1 / infrared a19 dac2_bout video and graphics c2 mux2_0 multiplexed io a20 vdd33 3.3 v power c3 gnd ground a21 gpio_23 general purpose i/o c4 dv1_data5 video and graphics a22 gpio_18 general purpose i/o c5 dv1_data0 video and graphics a23 nc c6 dv1_data4 video and graphics a24 ci_data3 channel interface c7 vdd33 3.3 v power a25 nc c8 dv1_data2 video and graphics a26 gnd ground c9 dac1_avdd3 dac analog pwr + gnd b1 nc c10 dac1_vref_in video and graphics b2 gnd ground c11 gpio_28 general purpose i/o b3 dv1_data6 video and graphics c12 gpio_27 general purpose i/o b4 dv1_data3 video and graphics c13 dac1_gref_out video and graphics b5 dv1_data1 video and graphics c14 dac1_rout video and graphics b6 nc c15 dac2_rout video and graphics b7 dac1_bout video and graphics c16 dac2_avdd1 dac analog pwr + gnd b8 vdd33 3.3 v voltage c17 nc b9 gpio_2 general purpose i/o c18 nc
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 22 of 39 stb02_sds_0327.fm.01 march 27, 2000 c19 dac2_avdd3 dac analog pwr + gnd e2 nc c20 nc e3 vdd33 3.3 v power c21 gpio_20 general purpose i/o e4 mux2_2 multiplexed io c22 vdd33 3.3 v power e23 vdd33 3.3 v power c23 gpio_5 general purpose i/o e24 ci_data7 channel interface c24 gnd ground e25 nc c25 ci_data0(msb) channel interface e26 ci_data4 channel interface c26 int1 interrupts f1 nc d1 mux2_1 multiplexed io f2 serial1/infrared_cts serial/infared d2 nc f3 reserved (tie to 3.3v) global d3 serial1/infrared_rts serial1 / infrared f4 vdd25 2.5 v power d4 gnd ground f23 vdd25 2.5 v power d5 vdd33 3.3 v power f24 nc d6 vdd25 2.5 v power f25 nc d7 nc f26 ci_clock channel interface d8 dac1_agnd2 dac analog pwr + gnd g1 vdd33 3.3 v power d9 gnd ground g2 gpio_11 general purpose i/o d10 dac1_avdd2 dac analog pwr + gnd g3 g_system_rst global d11 vdd25 2.5 v power g4 serial1/infrared_rxd serial/infared d12 vdd33 3.3 v power g23 ci_data2 channel interface d13 dac1_agnd0 dac analog pwr + gnd g24 nc d14 gnd ground g25 nc d15 dac2_gref_in video and graphics g26 ci_data6 channel interface d16 vdd25 2.5 v power h1 gpio_14 general purpose i/o d17 dac2_avdd2 dac analog pwr + gnd h2 nc d18 dac2_agnd2 dac analog pwr + gnd h3 vdd33 3.3 v power d19 gnd ground h4 gnd ground d20 gpio_19 general purpose i/o h23 nc d21 vdd25 2.5 v power h24 ci_data_enable channel interface d22 nc h25 nc d23 gnd ground h26 sd1_address9 sdram1 controller d24 ci_data1 channel interface j1 nc d25 nc j2 gpio_29 general purpose i/o d26 nc j3 nc e1 mux2_3 multiplexed io j4 nc signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 23 of 39 j23 gnd ground n26 sd1_cs0 sdram1 controller j24 vdd33 3.3 v power p1 da_bit_clock audio j25 sd1_address10 sdram1 controller p2 da_oversampling_clo ck audio j26 sd1_address8 sdram1 controller p3 mux3_2 multiplexed io k1 nc p4 vdd33 3.3 v power k2 nc p23 gnd ground k3 gpio_10 general purpose i/o p24 sd1_address2 sdram1 controller k4 nc p25 sd1_dqmh sdram1 controller k23 sd1_address6 sdram1 controller p26 gpio_4 general purpose i/o k24 sd1_address7 sdram1 controller r1 mux3_10 multiplexed io k25 sd1_address12 sdram1 controller r2 da_serial_data0 audio k26 nc r3 mux3_9 multiplexed io l1 nc r4 vdd33 3.3 v power l2 gpio_9 general purpose i/o r23 sd1_clk sdram1 controller l3 gpio_13 general purpose i/o r24 sd1_cas sdram1 controller l4 vdd25 2.5 v power r25 sd1_we sdram1 controller l23 vdd25 2.5 v power r26 vdd33 3.3 v power l24 sd1_address11 sdram1 controller t1 mux3_8 multiplexed io l25 sd1_address4 sdram1 controller t2 mux3_7 multiplexed io l26 sd1_address13(lsb) sdram1 controller t3 mux3_6 multiplexed io m1 vdd33 3.3 v power t4 vdd25 2.5 v power m2 gpio_12 general purpose i/o t23 vdd25 2.5 v power m3 da_iec_958 audio t24 sd1_dqml sdram1 controller m4 da_lr_channel_clock audio t25 sd1_data9 sdram1 controller m23 vdd33 3.3 v power t26 sd1_data7 sdram1 controller m24 sd1_address5 sdram1 controller u1 nc m25 sd1_address0 sdram1 controller u2 mux3_4 multiplexed io m26 sd1_address3 sdram1 controller u3 mux3_3 multiplexed io n1 i2c0_scl inter-integrated circuit u4 mux3_5 multiplexed io n2 gpio_15 general purpose i/o u23 sd1_data8 sdram1 controller n3 i2c0_sda inter-integrated circuit u24 sd1_data6 sdram1 controller n4 gnd ground u25 sd1_data5 sdram1 controller n23 vdd33 3.3 v power u26 sd1_data10 sdram1 controller n24 sd1_address1 sdram1 controller v1 mux3_1 multiplexed io n25 sd1_ras sdram1 controller v2 mux3_0 multiplexed io signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 24 of 39 stb02_sds_0327.fm.01 march 27, 2000 v3 vdd33 3.3 v power ab24 vdd33 3.3 v power v4 gnd ground ab25 mux1_0 multiplexed io v23 sd1_data12 sdram1 controller ab26 gpio_3 general purpose i/o v24 sd1_data4 sdram1 controller ac1 bi_cs3 bus interface v25 sd1_data3 sdram1 controller ac2 clk_vdda pll analog pwr + gnd v26 sd1_data11 sdram1 controller ac3 g_system_clock global w1 sc0_reset smart card interface 0 ac4 gnd ground w2 sc0_vcc_command smart card interface 0 ac5 bi_address17 bus interface w3 gpio_8 general purpose i/o ac6 vdd25 2.5 v power w4 sc0_io smart card interface 0 ac7 bi_address18 bus interface w23 gnd ground ac8 gnd ground w24 vdd33 3.3 v power ac9 bi_address12 bus interface w25 sd1_data13 sdram1 controller ac10 bi_address23 bus interface w26 sd1_data2 sdram1 controller ac11 vdd25 2.5 v power y1 sc0_detect smart card interface 0 ac12 bi_ready bus interface y2 sc0_clk smart card interface 0 ac13 gnd ground y3 nc ac14 vdd33 3.3 v power y4 gpio_6 general purpose i/o ac15 vdd33 3.3 v power y23 gpio_17 general purpose i/o ac16 vdd25 2.5 v power y24 sd1_data1 sdram1 controller ac17 bi_data9 bus interface y25 sd1_data14 sdram1 controller ac18 gnd ground y26 vdd33 3.3 v power ac19 bi_data28 bus interface aa1 gpio_7 general purpose i/o ac20 bi_data27 bus interface aa2 nc ac21 vdd25 2.5 v power aa3 nc ac22 vdd33 3.3 v power aa4 vdd25 2.5 v power ac23 gnd ground aa23 vdd25 2.5 v power ac24 int0 interrupts aa24 sd1_data15 sdram1 controller ac25 nc aa25 gpio_16 general purpose i/o ac26 mux1_2 multiplexed io aa26 sd1_data0 sdram1 controller ad1 int3 interrupts ab1 gpio_30 general purpose i/o ad2 int2 interrupts ab2 gpio_31 general purpose i/o ad3 gnd ground ab3 bi_cs2 bus interface ad4 bi_address14 bus interface ab4 vdd33 3.3 v power ad5 vdd33 3.3 v power ab23 mux1_1 multiplexed io ad6 bi_address19 bus interface signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 25 of 39 ad7 bi_address20 bus interface ae16 bi_data5 bus interface ad8 vdd33 3.3 v power ae17 bi_data6 bus interface ad9 bi_address22 bus interface ae18 bi_data8 bus interface ad10 bi_address9 bus interface ae19 bi_data0 bus interface ad11 bi_cs0 bus interface ae20 bi_data15 bus interface ad12 bi_wbe0 bus interface ae21 nc ad13 bi_data13 bus interface ae22 bi_data19 bus interface ad14 bi_data11 bus interface ae23 bi_data18 bus interface ad15 bi_data3 bus interface ae24 bi_data24 bus interface ad16 bi_data2 bus interface ae25 gnd ground ad17 bi_data1 bus interface ae26 bi_data23 bus interface ad18 vdd33 3.3 v power af1 gnd ground ad19 bi_data20 bus interface af2 bi_address31 bus interface ad20 nc af3 bi_address30 bus interface ad21 bi_data22 bus interface af4 bi_address15 bus interface ad22 bi_data25 bus interface af5 bi_address28 bus interface ad23 bi_data17 bus interface af6 bi_address27 bus interface ad24 gnd ground af7 vdd33 3.3 v power ad25 bi_data16 bus interface af8 bi_address25 bus interface ad26 bi_data31 bus interface af9 bi_address24 bus interface ae1 gnd ground af10 nc ae2 gnd ground af11 bi_address8 bus interface ae3 bi_address29 bus interface af12 vdd33 3.3 v power ae4 nc af13 bi_cs1 bus interface ae5 bi_address16 bus interface af14 bi_data12 bus interface ae6 nc af15 aud_vdda0 pll analog pwr + gnd ae7 bi_address26 bus interface af16 bi_data10 bus interface ae8 bi_address21 bus interface af17 nc ae9 bi_address11 bus interface af18 bi_data14 bus interface ae10 bi_address10 bus interface af19 bi_data7 bus interface ae11 bi_address13 bus interface af20 bi_data29 bus interface ae12 aud_vdda1 pll analog pwr + gnd af21 bi_data21 bus interface ae13 bi_oe bus interface af22 bi_data26 bus interface ae14 bi_rw bus interface af23 nc ae15 bi_data4 bus interface af24 bi_data30 bus interface signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 26 of 39 stb02_sds_0327.fm.01 march 27, 2000 af25 gnd ground af26 gnd ground signal pins sorted by pin number (continued) grid (pin) position signal group grid (pin) position signal group
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 27 of 39 stb0210x multiplexed i/o signal table stb0210x has four sets of multiplexed i/o signals: mux0, mux1, mux2, and mux3. at reset, the multiplexed i/o signals are tristated, unless noted. the muxtiplexed i/o can be selected by column in the following tables. for example, if input/output 1 is selected, input/output 2 and input/output 3 are not available. blank entries indicate reserved multiplexing. multiplexed i/o signal table - mux1 bit # input/output 1 i/o input/output 2 i/o input/output 3 00 edmac2_ack o ebm_holdack i/o ide_req i 01 edmac2_req i ebm_holdreq i/o ide_ack o 02 edmac2_eot i/o ebm_busreq i/o multiplexed i/o signal table - mux2 bit # input/output 1 i/o input/output 2 i/o 00 serial0/16550_txd o ssp_txd o 01 serial0/16550_rxd i ssp_rxd i 02 serial0/16550_cts i ssp_clk i 03 serial0/16550_rts o ssp_fs i/o multiplexed i/o signal table - mux3 bit # input/output 1 i/o input/output 2 i/o input/output 3 i/o input/output 4 i/o 00 hsp_data0 o serial1/infrare d_dsr (through gpio bit 31 alt rcv 2) i 01 hsp_data1 o serial1/infrare d_dtr o 02 hsp_data2 o rw_tms (through gpio bit 11 alt rcv 1 i rt_ts1e o 03 hsp_data3 o rw_tdi (through gpio bit 12 alt rcv 1) i rt_ts2e o 04 hsp_data4 o rw_tck (through gpio bit 13 alt rcv 1) i rt_ts3 o 05 hsp_data5 o rw_tdo o rt_ts4 o
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 28 of 39 stb02_sds_0327.fm.01 march 27, 2000 06 hsp_data6 o rw_halt (through gpio bit 15 alt rcv 1) i rt_ts5 o 07 hsp_data7 o serial0/16550_ds r (through gpio bit 5 alt rcv 3) i rt_ts6 o 08 hsp_clock o serial0/16550_dt r o 09 hsp_data_ enable o serial0/16550_dc d (through gpio bit 6 alt rcv 3) i 10 hsp_packet_ start o serial0/16550_ri (through gpio bit 8 alt rcv 3) i multiplexed i/o signal table - mux3 (continued) bit # input/output 1 i/o input/output 2 i/o input/output 3 i/o input/output 4 i/o
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 pin and i/o information page 29 of 39 general purpose i/o (gpio) the following table describes the gpio bits. for each gpio bit only one signal can be selected at a time. each table row lists the signal associated with each logical gpio bit number. the ?rst column lists the gpio bit number. the second column lists the signal connected as input or output to the ?rst alternate gpio multiplexer. the signal name is listed ?rst, followed by the signal description. the third column gives the direction of the signal listed in column 2. the same format is used for columns 4 through 7. blank entries indicate reserved gpio multiplexing. gpio bit number refers to the device gpio signal name, not the physical device pin number. after reset all gpios are programmed as inputs, with the exception of gpio0 bit 29 (pwm output), which defaults to an open-drain output, and gpio bit 14 (jtag tdo output), which defaults to an output (if bi_data[4] is set to 0 during reset). general purpose i/o bits bit # input/output mux 1 type input/output mux 2 type input/output mux 3 type 00 01 02 av_csync bi_cs4 i o gpt_freqgenout o int4 i 03 sys_clk o bi_cs5 o int5 i 04 edma c0_req i sd1_cs1 o serial0/16550_dtr o 05 edma c0_a ck o serial0/16550_dsr i 06 scp_txd o ci_packet_start i serial0/16550_dcd i 07 scp_rxd i ci_data_error i ts_bclken i 08 scp_clk o ts_req o serial0/16550_ri i 09 pwm0 o gpt_comp0 o gpt_capt0 bi_cs6 i o 10 pwm1 o gpt_comp1 o gpt_capt1 bi_cs7 i o 11 rw_tms i ssp_txd o bi_cs6 o 12 rw_tdi i ssp_rxd i bi_cs7 o 13 rw_tck i ssp_clk i int6 i 14 rw_tdo o ssp_fs i/o int7 i 15 r w_hal t i serial0/16550_clk - external serial0/16550 clock input i sys_clk o 16 bi_cs4 o 17 bi_cs5 o hsp_error o 18 dv_transparency_ gate i/o dv2_pixel_clock i serial1/infrared_clk - external serial1/infrared clock input i 19 ttx_req i/o dv2_vsync i/o
ibm39stb0210x stb0210x digital set-top box integrated controllers advance pin and i/o information page 30 of 39 stb02_sds_0327.fm.01 march 27, 2000 20 ttx_data i/o dv2_hsync i/o 21 dv2_data0 (msb) i/o int8 i 22 dv2_data1 i/o int9 i 23 dv2_data2 i/o 24 dv2_data3 i/o 25 dv2_data4 i/o 26 dv2_data5 i/o 27 dv2_data6 i/o 28 dv2_data7 i/o 29 denc_pwm_output o xpt_pwm_output o 30 edma c1_req bi_wbe2 i o serial1/infrared_dtr o 31 edma c1_a ck o serial1/infrared_dsr bi_wbe3 i o general purpose i/o bits (continued) bit # input/output mux 1 type input/output mux 2 type input/output mux 3 type
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 electrical information page 31 of 39 electrical information the following tables give the absolute ratings for various electrical characteristics. drivers/receivers four types of i/o drivers and receivers are used on the stb0210x device, as follows: . dc electrical characteristics the table, dc electrical characteristics, gives the absolute ratings for various electrical characteristics. the temperature is 70 c in all cases. i/o driver types driver/ receiver type characteristics used on i/o signals: bp3365 5 v tolerant, no pull-up or pull-down (external pull-up is required) g_system_reset, gpio[2], gpio[29], sc0_io, sc0_clk, sc0_detect, sc0_reset, sc0_vcc_command, bi_ready bp3335 5 v tolerant, no pull-up or pull-down (external pull-up is required) i2c0_sda, i2c0_scl bt3350pu 3.3 v i/o with pull-up bi_data[0:31] bt3365pu 3.3 v i/o with pull-up all other digital i/o signals dc electrical characteristics driver / receiver symbol parameter conditions min typ max units bp3335 v ih high level input voltage 2.00 5.50 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 17.0 ma 2.40 v v ol low level output voltage v cc = min, i ol = 11.0 ma 0.4 v bp3365 v ih high level input voltage 2.00 5.50 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 9.0 ma 2.40 v v ol low level output voltagec v cc = min, i ol = 6.0 ma 0.4 v 1. maximum v ih applies to overshoot only. 2. minimum v il applies to undershoot only.
ibm39stb0210x stb0210x digital set-top box integrated controllers advance electrical information page 32 of 39 stb02_sds_0327.fm.01 march 27, 2000 bt3350pu v ih high level input voltage 2.00 4.0 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 12.0 ma 2.40 v v ol low level output voltage v cc = min, i ol = 8.0 ma 0.4 v bt3365pu v ih high level input voltage 2.00 4.0 1 v v il low level input voltage -0.60 2 0.80 v v oh high level output voltage v cc = min, i oh = 9.0 ma 2.40 v v ol low level output voltage v cc = min, i ol = 6.0 ma 0.4 v bt3350pu, bt3365pu i i maximum input current v in = 0 v -250 m a bp3335, bp3365 i i maximum input current 0 m a n/a i cc supply current, 2.5 v v cc = max tbd ma n/a i cc330 supply current, 3.3 v v cc330 = max tbd ma all c i input capacitance v cc = nom, v i = nom 2.6 pf all esd electro static discharge tbd tbd v n/a pd power dissipation 2.5 w dc electrical characteristics (continued) driver / receiver symbol parameter conditions min typ max units 1. maximum v ih applies to overshoot only. 2. minimum v il applies to undershoot only.
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 electrical information page 33 of 39 the absolute maximum ratings in the following table are stress ratings only. operation at or beyond these maximum ratings may cause permanent damage to the device. . operating conditions the stb0210x digital set-top box integrated controller can interface to either 3.3 v or 5 v technologies. 5 v interfaces are supported only for drivers/receivers supporting 5 v tolerance (see drivers/receivers ). the range for supply voltages is specified for five-percent margins relative to a nominal 2.5 v and 3.3 v power supply. note: device operation beyond the conditions specified in the table below is not recommended. extended operation beyond the recommended conditions may affect device reliability. power considerations power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. recommended connections power and ground pins should all be connected to separate power and ground planes in the circuit board to which the stb0210x is mounted. unused input pins must be tied inactive, either high or low. absolute maximum ratings parameter maximum rating supply voltage with respect to gnd, 2.5 v supply 3.0 v supply voltage with respect to gnd, 3.3 v supply 3.9 v case temperature under bias tbd storage temperature -65 c to 150 c recommended operating conditions symbol parameter min max unit v cc supply voltage, 2.5 v 2.38 2.62 v v cc330 supply voltage, 3.3 v 3.14 3.47 v t a operating free air temperature 0 70 c
ibm39stb0210x stb0210x digital set-top box integrated controllers advance electrical information page 34 of 39 stb02_sds_0327.fm.01 march 27, 2000 i/o timing diagrams ac speci?cation timings are being developed and will be added when available. they should be similar to stb03xxx. note: recommended connections for analog i/o pins dac1_avdd0 dac1_avdd1 dac1_avdd2 dac1_avdd3 dac2_avdd0 dac2_avdd1 dac2_avdd2 dac2_avdd3 dac1_gref_out dac2_gref_out dac1_rref_out dac2_rref_out dac1_bref_out dac2_bref_out clk_vdda aud_vdda0 aud_vdda1 .1 mf b12 d10 b11 c9 a14 d17 c16 c19 .1 mf .1 mf .1 mf .1 mf 22 mf 784 .1 mf .1 mf 5 k 1.2 mh 2.5 v 1.2 mf 2.5v 1 nh 2.5 v c13 d13 ac2 a7 (for a 75 w dac output load) 1 nf 1 nf 784 a9 b18 1 nf 1 nf b19 af15 ae12
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 electrical information page 35 of 39 additional timing information interface timing information iic compliant with philips semiconductors i 2 c specification, dated 1995. interface is asynchronous direct connect smart card (sc) compatible with iso/iec 7816-3. interface is asynchronous direct connect serial0/16550 functionally identical to national semiconductor ns16450 in character mode (after reset). interface is asynchronous external transceiver logic is required serial1/infrared functionally identical to ibm powerpc403 ? serial port unit (spu) (after reset). compatible with the irda specification 1.1 irda 1.0 sir with data rates up to 115.2 kbps irda 1.1 fir with data rates up to 1.152 mbps interface is asynchronous external transceiver logic is required external interrupts inputs are asynchronous dma external dma request inputs are asynchronous gpt capture timer inputs are asynchronous external bus master interface is asynchronous riscwatch compatible with ibm riscwatch probe direct connect to probe contact your ibm applications engineer for more information risctrace compatible with ibm risctrace probe direct connect to probe contact your ibm applications engineer for more information
ibm39stb0210x stb0210x digital set-top box integrated controllers advance mechanical information page 36 of 39 stb02_sds_0327.fm.01 march 27, 2000 mechanical information package diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a 1.27 31.75 35 af ae- ad ac ab aa y w v u t r p n m l k j h g f e d c b a b 1.27 31.75 35 0. 20 m top of package (bga side down) oem p/n 0.15 c c 0.25 c (352x ? 0.75 0.15 solder ball c ? 0.30 ? 0.15 c a b m ibm p/n xxxxxxx date code ibm39 stb0210x xxx xxx powerpc a digital set-top box integrated controller zzwwmmmm bottom of package (bga side up)
ibm39stb0210x advance stb0210x digital set-top box integrated controllers stb02_sds_0327.fm.01 march 27, 2000 development support page 37 of 39 development support with ibm tools and the ibm powerpc embedded tools program, you receive the support you need to develop and debug your stb applications quickly. ibm tools ibm offers windows 95/98 - hosted development tools for stb applications that include: ? stb and processor reference design and evaluation kits, including board, compiler, debugger, rom source, schematics, etc. ? riscwatch debugger, with in-circuit, rom monitor, rtos-aware debugging and real-time non-invasive trace capability ? metaware high c/c++ compiler, highly optimized for the powerpc processors debug the stb0210x facilitates development through its jtag test access port. with ibm riscwatch or other third-party debugger on a workstation, you can single-step the processor and interrogate the internal processor state. additionally, the real-time debug port supports tracing the executed instruction stream out of the instruction cache. the trace status signals provide trace information in real-time instruction trace debug mode. this mode does not alter the performance of the processor. third-party tool support through the ibm powerpc embedded tools program, you have access to hundreds of tools offered by over 75 industry-leading vendors. often, the tools you currently use support powerpc embedded processor prod- ucts, such as the ibm stb010xx digital set-top box integrated controllers. for a list of the tools that are offered, visit ibms tool support web page at: http://www.chips.ibm.com/products/powerpc/tools/ note: this document contains information on products in the sampling and/or initial production phases of development. this information is subject to change without notice. verify with your ibm field applications engineer that you have the latest version of this document before finalizing a design.
ibm39stb0210x stb0210x digital set-top box integrated controllers advance revision log page 38 of 39 stb02_sds_0327.fm.01 march 27, 2000 revision log revision contents of modi?cation march 24, 2000 initial release (revision 00). march 27, 2000 update to gpio table (revision 01)
copyright and disclaimer copyright international business machines corporation 2000. all rights reserved printed in the united states of america february 2000 the following are trademarks of international business machines corporation in the united states, or other countries, or both: ibm ibm logo coreconnect powerpc logo powerpc 401 windows is a trademark of microsoft corporation in the united states and/or other countries. other company, product, and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm's product specifications or warran- ties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is pre- sented as an illustration. the results obtained in other operating environments may vary. product name is subject to change. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com stb02_sds_0327.fm.01 march 27, 2000

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